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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
6.
mmb 30002 40 ; power down TX AA
7.
mmb 30003 40 ; power down RX AA
8.
mmb 30012 40 ; power down TX AB
9.
mmb 30013 40 ; power down RX AB
10.
mmb 30022 40 ; power down TX AC
11.
mmb 30023 40 ; power down RX AC
12.
mmb 30032 40 ; power down TX AD
13.
mmb 30033 40 ; power down RX AD
14.
mmb 30103 30 ; BA RX 1/1 rate, alarm ovrd, no lnk FSM,8b10br
15.
mmb 30113 30 ; BB RX 1/1 rate, alarm ovrd, no lnk FSM,8b10br
16.
mmb 30123 30 ; BC RX 1/1 rate, alarm ovrd, no lnk FSM,8b10br
17.
mmb 30133 30 ; BD RX 1/1 rate, alarm ovrd, no lnk FSM,8b10br
18.
mmb 30102 31 ; BA TX 1/1 rate, 8b10bT + full pre-emphasis
19.
mmb 30112 31 ; BB TX 1/1 rate, 8b10bT + full pre-emphasis
20.
mmb 30122 31 ; BC TX 1/1 rate, 8b10bT + full pre-emphasis
21.
mmb 30132 31 ; BD TX 1/1 rate, 8b10bT + full pre-emphasis
22.
mmb 30900 FF ; enable BYTSYNC; lock PLL to data
23.
mmb 30933 01; enable characterization pins
24.
mmb 30920 01 ; XAUI mode
25.
mmb 30921 00 ; don’t bypass chnl align. On B
26.
mmb 30104 40 ; BA MASK ALARM, NO TESTEN
27.
mmb 30114 40 ; BB MASK ALARM, NO TESTEN
28.
mmb 30124 40 ; BC MASK ALARM, NO TESTEN
29.
mmb 30134 40 ; BD MASK ALARM, NO TESTEN
30.
mmb 30901 00 ; NO LOOPBACK, Allow WD align for BA BB BC BD
31.
mmb 30910 0F ; Enable Ch. Align. for BA BB BC & BD
32.
mmb 30911 55 ; FMPU SYNC MODE FOR BA BB BC BD (QUAD)
33.
PROGRAM OTHER FPGA REGISTERS HERE IF NECESSARY
34.
dmb 30904 1 ; read XAUI states (before resync)
35.
dmb 30905 1 ; read word aligner status and ch248
36.
dmb 30914 1 ; read OOS status
37.
mmb 30105 64 ; Perform another software reset
38.
dmb 30105 1 ; wait for a while before removing reset
39.
dmb 30105 1 ; wait for a while before removing reset
40.
mmb 30105 44 ; remove software reset
41.
mmb 30910 00 ; perform word align
42.
mmb 30910 0F ;
43.
mmb 30920 01 ; perform resync
44.
mmb 30920 03
Automatic SERDES Channel Alignment
The XGXS IP core supports automatic XAUI word and quad channel alignment resynchronization upon loss of
sync at the XAUI interface. Automatic resynchronization is enabled/disabled by setting/clearing XGXS register bit
4.8002.15 via the MDIO interface (see the Functional Description section). The resynchronization procedure
includes the following steps:
1. Perform a word DEMUX alignment on all channels by:
Writing 0x0F to ORT82G5 embedded core register 30910.
Writing 0xFF to ORT82G5 embedded core register 30910.
2. Do a four channel alignment resynchronization by:
Writing 0x01 to ORT82G5 embedded core register 30920.
Writing 0x03 to ORT82G5 embedded core register 30920.
15
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